1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive structures, such as conductive lines/vias, using a sacrificial liner layer during the process of forming such conductive structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To improve the operating speed of field effect transistors (FETs), and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs and the overall functionality of the circuit. Further scaling (reduction in size) of the channel length of transistors is anticipated in the future. While this ongoing and continuing decrease in the channel length of transistor devices has improved the operating speed of the transistors and integrated circuits that are formed using such transistors, there are certain problems that arise with the ongoing shrinkage of feature sizes that may at least partially offset the advantages obtained by such feature size reduction. For example, as the channel length is decreased, the pitch between adjacent transistors likewise decreases, thereby increasing the density of transistors per unit area. This scaling also limits the size of the conductive contact elements and structures, which has the effect of increasing their electrical resistance. In general, the reduction in feature size and increased packing density makes everything more crowded on modern integrated circuit devices.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same level on which the circuit elements, such as transistors, are manufactured. Rather, modern integrated circuit products have multiple so-called metallization layer levels that, collectively, contain the “wiring” pattern for the product, i.e., the conductive structures that provide electrical connection to the transistors and the circuits, such as conductive vias and conductive metal lines. In general, the conductive metal lines are used to provide intra-level (same level) electrical connections, while inter-level (between levels) connections or vertical connections are referred to as vias. In short, the vertically oriented conductive via structures provide the electrical connection between the various stacked metallization layers. Accordingly, the electrical resistance of such conductive structures, e.g., lines and vias, becomes a significant issue in the overall design of an integrated circuit product, since the cross-sectional area of these elements is correspondingly decreased, which may have a significant influence on the effective electrical resistance and overall performance of the final product or circuit.
Improving the functionality and performance capability of various metallization systems has also become an important aspect of designing modern semiconductor devices. One example of such improvements is reflected in the increased use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than about 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias. The use of low-k dielectric materials tends to improve the signal-to-noise ratio (S/N ratio) by reducing cross-talk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric materials can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials.
Copper is a material that is difficult to directly etch using traditional masking and etching techniques. Thus, conductive copper structures, e.g., conductive lines or vias, in modern integrated circuit devices are typically formed using known single or dual damascene techniques. In general, the damascene technique involves (1) forming a trench/via in a layer of insulating material, (2) depositing one or more relatively thin barrier or liner layers (e.g., TiN, Ta, TaN), (3) forming copper material across the substrate and in the trench/via, and (4) performing a chemical mechanical polishing process to remove the excess portions of the copper material and the barrier layer(s) positioned outside of the trench/via to define the final conductive copper structure. The copper material is typically formed by performing an electrochemical copper deposition process after a thin conductive copper seed layer is deposited by physical vapor deposition on the barrier layer.
However, as everything becomes more crowded on an integrated circuit product, problems may arise when employing traditional damascene techniques. One such problem will be discussed with reference to FIGS. 1A-1C, which depict an illustrative example of a trench-first metal hard mask type damascene process, wherein the trench is first patterned on to the hard mask and then the via lithography/etching processes are performed. FIG. 1A depicts an integrated circuit product 10 comprised of a plurality of illustrative conductive structures 12, e.g., conductive lines, formed in a layer of insulating material 14. An etch stop layer 16 is formed above the layer of insulating material 14. The layers 14, 16 and the conductive structures 12 may all be considered to be part of a metallization layer 15 of an integrated circuit product. Electrical connections are to be made to the conductive structures 12. Thus, another metallization layer 17 is formed above the metallization layer 15. In the depicted example, formation of the metallization layer 17 involves formation of a layer of insulating material 18 and an etch mask 19 comprised of first and second layers of material 20, 22. In one example, the layers of insulating material 14, 18 may be layers of so-called low-k (k value less than about 3.3) insulating material, the layer 16 may be a layer of silicon nitride, the layer 20 may be a TEOS based layer of silicon dioxide, and the layer 22 may be a hard mask made of a material such as titanium nitride.
FIG. 1A depicts the product 10 after several process operations have been performed. First, using known photolithography and etching techniques, a patterned photo-resist mask (not shown) was formed above the product 10 and the mask layer 19 was patterned as depicted. Thereafter, the photoresist mask was removed and one or more etching processes were performed through the patterned mask layer 19 to form the depicted via openings 24 through the layers 18, 16 so as to expose the underlying conductive structures 12. The via openings 24 may have a square, rectangular or round configuration when viewed from above.
FIG. 1B depicts the product 10 after another etching process was performed to form a trench for a conductive metal line that will run in the direction indicated by the double arrows 21. As depicted, a great deal of the region 18A of insulating material 18 between the via openings 24 is consumed during this line-etch process. More specifically, after the line/trench etch process depicted in FIG. 1B, the sidewalls of the region 18A are positioned at a very shallow angle 25 due to the excessive consumption of the region 18A of insulating material 18 between the via openings 24 during the line-etch process.
FIG. 1C depicts the product 10 after a barrier layer 28 and bulk copper material 26 have been formed above the device and subjected to one or more chemical mechanical planarization (CMP) processes using techniques well known to those skilled in the art and briefly described above. Such processes also result in the removal of the layer 22. Unfortunately, due to the excess consumption of the region 18A of the insulating material, and the resulting shallow angle 25 of the sidewalls of the remaining portion of the region 18A, problems may arise. Given the increased packing densities and crowding noted above, the space 30 between adjacent conductive structures, e.g., the conductive lines 12, is very small and an important design rule that is tightly controlled. However, in the case where there is the depicted excessive consumption of the region 18A, the distance 32 between one of the conductive structures 12 in the metallization layer 15 may be less than the allowable distance 30 as dictated by the design rules. Such a situation may lead to unacceptable performance degradation, e.g., an undesirable increase in cross-talk, a premature breakdown in the insulating material along the path indicated by the double arrows 32, which might lead to highly undesirable electrical shorts and/or circuit failure.
The present disclosure is directed to various methods of forming conductive structures, such as conductive lines/vias, using a sacrificial liner layer that may solve or at least reduce some of the problems identified above.